CCntsGlbls Class class CCntsGlbls CPUId Funct Set RAX register value. CPURep Funct Report number of cores and clock freq. Carry Funct Number of PCI buses. Fs Funct Invalidate page at addr inst. GetPCIDevInfo Funct { GetRAX Funct Number of PCI buses. GetRBP Funct Number of PCI buses. GetRFlags Funct See ::/Demo/Carry.HC GetRSP Funct See ::/Demo/Carry.HC Gs Funct only used during Core0StartMP IntEntryGet Funct Get interrupt vector. IntEntrySet Funct Set interrupt vector. See IDTET_IRQ. LXchgI64 Funct Set RBP register value. LXchgU16 Funct Set RFlags register value. LXchgU32 Funct Set RSP register value. LXchgU8 Funct Do CPUID inst. MaskIrq Funct { PCILookUpDevs Funct { PCIRep Funct Report description of PCI devices. PCIScanBus Funct Returns a queue of PCI devices attached to a single bus Pop Funct See ::/Demo/Carry.HC Push Funct Get RAX register value. RouteIrq Funct { SetMSR Funct Locked eXchange I64s. SetRAX Funct Get RBP register value. SetRBP Funct Get RFlags register value. SetRFlags Funct Get RSP register value. SetRSP Funct Pop value from stk. SysHlt Funct Locked eXchange U16s. XchgI64 Funct Locked eXchange U32s. XchgU16 Funct Locked eXchange U8s. XchgU32 Funct Model Specific Reg See MSRs. XchgU8 Funct Model Specific Reg See MSRs.
Processor CLFlush Funct eXchange U32s. sys_cache_line_widthGlbVar _extern SYS_GDT CGDT sys_gdt;
Processor/Cache InU16 Funct _extern SYS_FRAME_BUFFER U32 sys_frame_buffer; InU32 Funct _extern SYS_VBE_MODE_PITCH U16 sys_vbe_mode_pitch; InU8 Funct _extern VBE_VID_MODES U32 vbe_vid_modes[32]; OutU16 Funct #help_index "I/O;Processor/IO Port" OutU32 Funct #help_index "I/O;Processor/IO Port" OutU8 Funct Read U16 from I/O port. RepInU16 Funct Read U8 from I/O port. RepInU32 Funct Write U32 to I/O port. RepInU8 Funct Repeated read U16 from I/O port. RepOutU16 Funct Repeated read U32 from I/O port. RepOutU32 Funct Repeated read U8 from I/O port. RepOutU8 Funct Repeated write U16 to I/O port.
Processor/IO Port InvlPg Funct CPU's Cache line width. mem_page_size GlbVar I64 sys_cache_line_width; //CPU's Cache line width.
Processor/Page Tables